I've spent too much time on this already, especially since it's still out there in "pipe dream" territory.
Anyway, for future reference, I've decided to go with the Xilinx Spartan 3-400. Big enough for most applications, it's also the largest QFP format chip, so a user doesn't need either an IR oven or a hot air rework station (I want to buy/build both), so others can work this design.
It's fully supported, development hardware is available for low cost (Digilent-400 version of the starter board), and hopefully the free simulator will run it.
And hopefully I can run it off of batteries. One current idea is to build a tiered design (similar to PC/104). Fixed size (square, circuilar is considered for sealed tube applications). Radially symmetrical, it'll have 4 digital voltage busses (GND, 1.8V, 2.5V, 3.3V, 5V), 4 analog ground busses (AGND, 5V Regulated, Unregulated). There will also be each bank brought out to a databus. Only those components that need access to all the databusses (like the FPGA) will be connected to all of them. All other boards will have passthroughs for the signals, and be connected to only one databus. If multiple FPGA's need to be mounted, a spacer board that passes only one bus through (and all power lines) will be required. Turning any board will just put the sensor on a different bus without any major bus arbitration (important for high speed apps like 200MSPS ADC's). This means that for "generic" boards, the most that can be used are 4, one per bus block. Custom boards may be able to use a CPLD and a jumper to split the busses into inside and outside, or left and right, etc. to at least double the possible board count.
As soon as I remember my FTP passwords, I'll upload a GIF to illustrate, and a possible board "stack" idea (Digital camera control and DSP or a radar stack).
Anyway, this is going on hold. I'd love to spend the $100-$200 and get everything I want, but my R/C core is waiting.
Basic board layout
Generic ADC sensor stack