Monday, January 10, 2005

Silly Scope - Evolution to DataStack

This isn't a true evolution per se, but an extension I've been thinking about. I always wanted to loft some good hardware in my rockets, and the stack makes it strong enough and dense enough to do in a small-ish rocket.

A circular format of the boards will let us fit a bit more on them for the same hole spacing. I'm thinking of moving away from the four quadrant design to a two half design. Two digital power rails, two analog power rails, two pin grids. This will result in the need to control what uses what datalines to have more than 2 boards attached. A new addition will be a JTAG rail. This, when combined with a DIP or jumper on each board, will allow a single JTAG cable to program the entire stack. Going with 2 hookups leaves more space and "stack access" on each side for airflow or other situations (like access to a CF card slot).

Now, for the addon boards. Barring low latency parts like a SRAM/SDRAM board, all other boards will have a CPLD onboard. Probably a Coolrunner II. They can interface 1.5V to 3.3V and act like logic shifters, and also implement high speed interfaces (simplifying the databus to a single voltage requirement). I still plan to hook up only half the bus to the CPLD to keep two independent busses. A CPLD on each board will simplify reconfiguration for different stack designs. This does raise the cost a bit, though. The flexibility and I/O standardization is worth it, though. It also lets those do PCI or similar bus standards for those who want a true databus as opposed to my partitioned databus. Only other problem is that to get enough pins, the CPLD may have the same packaging as the FPGA!

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