Mid level cards will be built similar to the Bitscope. A PIC for communication with the databus (and identifying itself, housekeeping, etc), a CPLD doing the ADC interfacing and data dumping to the capture SRAM. Also logic analyzer (again, Bitscope compatible PODs perhaps). I MAY base the databus on standard 3.3V PCI, which many CPLDs can be used as the data bus conversion, or maybe ISA (ditto).
High level cards will be a beefier version. PIC or maybe dsPIC for the housekeeping, CPLD for bus buffering, Xilinx Spartan3 (or maybe the Cyclone II from Altera) for a strong but inexpensive system. It's gotta be able to keep up with 100-200MSPS at 8-14 bit from 1 or 2 ADC's (not certain yet). I'm avoiding large ball grid/pin grids as you really need multilayer for that, limiting me to the PQFP-208's package, so the largest Spartan3 I can use is the 400,000 gate version. That gives us over 256k of buffer RAM onboard, which is as deep as the Midline Bitscope-310.
Now, the Spartan can do DDR RAM speeds, and a max speed of 326MHz, which should be fast enough to get the data out. There are DDR controllers out there. However, DDR DIMM's are 168 pins, which would devour ALL my I/O (141?). So, custom memory boards and individual chips are required. Easy enough, Hot air rework station and cheap DDR-333 DIMMs give me the RAM I need.
So, what's the backplane providing? I'm thinking:
- 16-32 bit bidirectional data path.
- Card Select
- Digital Ground
- Analog Ground
- Digital Power (5V)
- Analog Power (24V?)
- Capture Trigger Start (single signal)
- Capture Sync Line (continuous capture sync)
The card's will have to attenuate their power supplies down via linear regulators to what's required for the boards themselves. Although this wastes power, it'll provide a cleaner connection, reducing interference from adjacent lines. The analog power is designed to be attenuated down, as it is very susceptible to digital noise.
Now, back to looking through the Spartan3 spec PDF...